ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 173

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.2.5
16.2.5.1
16.2.5.2
7647G–AVR–09/11
Errors
Error at Message Level
Error at Bit Level
The bus access conflict is resolved during the arbitration field mostly over the identifier value.
If a data frame and a remote frame with the same identifier are initiated at the same time, the
data frame prevails over the remote frame (c.f. RTR bit).
Figure 16-4. Bus Arbitration
The CAN protocol signals any errors immediately as they occur. Three error detection mecha-
nisms are implemented at the message level and two at the bit level:
• Cyclic Redundancy Check (CRC)
• Frame Check
• ACK Errors
• Monitoring
• Bit Stuffing
The CRC safeguards the information in the frame by adding redundant check bits at the
transmission end. At the receiver these bits are re-computed and tested against the
received bits. If they do not agree there has been a CRC error.
This mechanism verifies the structure of the transmitted frame by checking the bit fields
against the fixed format and the frame size. Errors detected by frame checks are
designated "format errors".
As already mentioned frames received are acknowledged by all receivers through positive
acknowledgement. If no acknowledgement is received by the transmitter of the message
an ACK error is indicated.
The ability of the transmitter to detect errors is based on the monitoring of bus signals.
Each node which transmits also observes the bus level and thus detects differences
between the bit sent and the bit received. This permits reliable detection of global errors
and errors local to the transmitter.
The coding of the individual bits is tested at bit level. The bit representation used by CAN is
"Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding.
The synchronization edges are generated by means of bit stuffing.
CAN bus
TXCAN
node B
TXCAN
node A
SOF
SOF
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Atmel ATmega16/32/64/M1/C1
Arbitration lost
Node A loses the bus
Node B wins the bus
RTR IDE
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