ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 65
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ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
- Current page: 65 of 367
- Download datasheet (7Mb)
7647G–AVR–09/11
Figure 9-3.
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows t
be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay t
Figure 9-4.
Figure
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
Synchronization when Reading an Externally Applied Pin value
Synchronization when Reading a Software Assigned Pin Value
9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
PINxn
r17
r16
r17
pd
out PORTx, r16
through the synchronizer is 1 system clock period.
Atmel ATmega16/32/64/M1/C1
XXX
pd,max
and t
t
pd, max
pd,min
0x00
0x00
XXX
nop
, a single signal transition on the pin will
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
0xFF
0xFF
65
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