ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 314

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ATMEGA64M1-15MZ

Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64M1-15MZ

Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details
25.9.2
314
Atmel ATmega16/32/64/M1/C1
Data Polling Flash
To program and verify the ATmega16/32/64/M1/C1 in the serial programming mode, the fol-
lowing sequence is recommended (See four byte instruction formats in
When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value 0xFF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be
written. Note that the entire page is written simultaneously and any address within the page
can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when pro-
gramming this value, the user will have to wait for at least t
next page. As a chip-erased device contains 0xFF in all locations, programming of addresses
that are meant to contain 0xFF, can be skipped. See
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte
5. The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
at a time by supplying the 6 LSB of the address and data together with the Load Pro-
gram Memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram Memory Page is stored by loading the Write Program Memory Page instruction
with the 8 MSB of the address. If polling is not used, the user must wait at least
t
gramming interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user
must wait at least t
chip erased device, no 0xFFs in the data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
WD_FLASH
CC
power off.
before issuing the next page. (See
WD_EEPROM
CC
and GND while RESET and SCK are set to “0”. In some
before issuing the next byte. (See
Table
Table 25-16
25-16.) Accessing the serial pro-
WD_FLASH
for t
Table
before programming the
WD_FLASH
Table
25-16.) In a
25-17):
value.
7647G–AVR–09/11

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