ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 256
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ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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18.11.3
256
Atmel ATmega16/32/64/M1/C1
Amplifier 2 Control and Status register – AMP2CSR
• Bit 3 – AMPCMP1: Amplifier 1 - Comparator 1 connection
Set this bit to connect the amplifier 1 to the comparator 1 positive input. In this configuration
the comparator clock is twice amplifier clock.
Clear this bit to normally use the Amplifier 1.
• Bit 2:0 – AMP1TS2,AMP1TS1, AMP1TS0: Amplifier 1 Clock Source Selection Bits
In accordance with the Table 18-11, these 3 bits select the event which will generate the clock
for the amplifier 1. This clock source is necessary to start the conversion on the amplified
channel.
Table 18-11. AMP1 Clock Source Selection
Bit
Read/Write
Initial Value
• Bit 7 – AMP2EN: Amplifier 2 Enable Bit
Set this bit to enable the Amplifier 2.
Clear this bit to disable the Amplifier 2.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
Warning: Always clear AMP2TS0:1 when clearing AMP2EN.
• Bit 6 – AMP2IS: Amplifier 2 Input Shunt
Set this bit to short-circuit the Amplifier 2 input.
Clear this bit to normally use the Amplifier 2.
• Bit 5, 4 – AMP2G1, 0: Amplifier 2 Gain Selection Bits
These 2 bits determine the gain of the amplifier 2.
The different setting are shown in
AMP1TS2
0
0
0
0
1
1
1
1
AMP1TS1
0
0
1
1
0
0
1
1
AMP2EN
R/W
7
0
AMP2IS
R/W
AMP1TS0
0
1
0
1
0
1
0
1
6
0
AMP2G1
R/W
Table
5
0
Clock Source
ADC Clock/8
Timer/Counter0 Compare Match
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
PSC Module 0 Synchronization Signal (PSS0)
PSC Module 1 Synchronization Signal (PSS1)
PSC Module 2 Synchronization Signal (PSS2)
18-12.
AMP2G0
R/W
4
0
AMPCMP2
R/W
3
0
AMP2TS2
R/W
2
0
AMP2TS1
R/W
1
0
AMP2TS0
R/W
0
0
7647G–AVR–09/11
AMP2CSR
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