ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 266
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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20.4.3
266
Atmel ATmega16/32/64/M1/C1
Analog Comparator 2 Control Register – AC2CON
In case ICES1 bit
the rising edge of AC1O is the capture/trigger event of the Timer/Counter1, in case ICES1 is
set to zero, it is the falling edge which is taken into account.
Clear this bit to disable this function. In this case, no connection between the Analog Compar-
ator and the input capture function exists.
• Bit 2, 1, 0– AC1M2, AC1M1, AC1M0: Analog Comparator 1 Multiplexer register
These 3 bits determine the input of the negative input of the analog comparator.
The different setting are shown in
Table 20-4.
Bit
Read/Write
Initial Value
• Bit 7– AC2EN: Analog Comparator 2 Enable Bit
Set this bit to enable the analog comparator 2.
Clear this bit to disable the analog comparator 2.
• Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit
Set this bit to enable the analog comparator 2 interrupt.
Clear this bit to disable the analog comparator 2 interrupt.
• Bit 5, 4– AC2IS1, AC2IS0: Analog Comparator 2 Interrupt Select bit
These 2 bits determine the sensitivity of the interrupt trigger.
The different setting are shown in
Table 20-5.
AC1M2
0
0
0
0
1
1
1
1
AC2IS1
0
0
1
1
Analog Comparator 1 negative input selection
Interrupt sensitivity selection
AC2IS0
0
1
0
1
AC1M1
0
0
1
1
0
0
1
1
AC2EN
R/W
7
0
(“Timer/Counter1 Control Register B – TCCR1B” on page
AC2IE
R/W
6
0
Description
Comparator Interrupt on output toggle
Reserved
Comparator interrupt on output falling edge
Comparator interrupt on output rising edge
AC1M0
0
1
0
1
0
1
0
1
AC2IS1
R/W
Table
Table
5
0
20-4.
18-7.
AC2IS0
Description
“Vref”/6.40
“Vref”/3.20
“Vref”/2.13
“Vref”/1.60
Bandgap (1.1V)
DAC result
Analog Comparator Negative Input (ACMPM pin)
Reserved
R/W
4
0
3
0
-
-
AC2M2
R/W
2
0
AC2M1
R/W
1
0
AC2M0
132) is set high,
R/W
0
0
7647G–AVR–09/11
AC2CON
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