ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 155

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

14.16.9
7647G–AVR–09/11
PSC Module n Input Control Register – PMICn
• Bit 4:3:2 – SWAPn: SWAP Funtion Select (not implemented in ATmega32M1 up to
When this bit is set; the channels PSCOUTnA and PSCOUTnB are exchanged. This allows to
invert the waveforms of both channels at one time.
• Bit 1 – PCCYC: PSC Complete Cycle
When this bit is set, the PSC completes the entire waveform cycle before halt operation
requested by clearing PRUN.
• Bit 0 – PRUN : PSC Run
Writing this bit to one starts the PSC.
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B.
The 2 blocks are identical, so they are configured on the same way.
• Bit 7 – POVENn : PSC Module n Overlap Enable
Set this bit to disactivate the Overlap Protection. See the Section “Overlap Protection”,
page 143.
• Bit 6 – PISELn : PSC Module n Input Select
Clear this bit to select PSCINn as module n input.
Set this bit to select Comparator n output as module n input.
• Bit 5 –PELEVn : PSC Module n Input Level Selector
When this bit is clear, the low level of selected input generates the significative event for fault
function.
When this bit is set, the high level of selected input generates the significative event for fault
function.
• Bit 4 – PFLTEn : PSC Module n Input Filter Enable
Setting this bit (to one) activates the Input Noise Canceler. When the noise canceler is acti-
vated, the input from the input pin is filtered. The filter function requires four successive equal
valued samples of the input pin for changing its output. The Input is therefore delayed by four
oscillator cycles when the noise canceler is enabled.
• Bit 3 – PAOCn : PSC Module n 0 Asynchronous Output Control
When this bit is clear, Fault input can act directly to PSC module n outputs A & B. See
Section “PSC Input Configuration”, page 146.
• Bit 2:0 – PRFMn2:0: PSC Module n Input Mode
These three bits define the mode of operation of the PSC inputs.
Bit
Read/Write
Initial Value
revision C)
POVENn
R/W
7
0
PISELn
R/W
6
0
PELEVn
R/W
5
0
Atmel ATmega16/32/64/M1/C1
PFLTEn
R/W
4
0
PAOCn
R/W
3
0
PRFMn2
R/W
2
0
PRFMn1
R/W
1
0
PRFMn0
R/W
0
0
PMICn
155