DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 173
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 173 of 907
- Download datasheet (6Mb)
Wait Modes in Areas Where Wait-State Controller is Enabled
External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn =
1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, as selected by
bits WMS1 and WMS0. Bits WMS1 and WMS0 apply to all areas, so all areas in which the wait-
state controller is enabled operate in the same wait mode.
Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states
(T
clock ( ) in the last of these wait states, an additional wait state is inserted. If the WAIT pin
remains low, wait states continue to be inserted until the WAIT signal goes high.
Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
If the wait count is 0, this mode operates in the same way as pin wait mode 0.
Figure 6.13 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional
wait state is inserted by WAIT input.
W
) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system
Read
access
Write
access
Note:
*
Arrows indicate time of sampling of the
WAIT
Address bus
AS
RD
Data bus
HWR, LWR
Data bus
pin
Figure 6.13 Pin Wait Mode 1
T
1
T
WAIT
2
pin.
External address
Inserted by
wait count
Write data
Write data
T
Rev. 7.00 Sep 21, 2005 page 147 of 878
W
*
Inserted by
WAIT
T
W
signal
*
Section 6 Bus Controller
Read data
T
3
REJ09B0259-0700
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