DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 686

• Manufacturer Part Number: DF3048X16V
• Description: MCU 5V 128K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Clock Pulse Generator
20.5
The frequency divider divides the duty-adjusted clock signal to generate the system clock ( ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
20.5.1
Table 20.4 summarizes the frequency division register.
Table 20.4 Frequency Division Register
Address*
H'FF5D
Note: * The lower 16 bits of the address are shown.
20.5.2
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: Read-only bits, always read as 1.
Rev. 7.00 Sep 21, 2005 page 660 of 878
REJ09B0259-0700
pin.
Bit
Initial value
Read/Write
Frequency Divider
Register Configuration
Division Control Register (DIVCR)
Name
Division control register
—
—
7
1
—
—
6
1
Reserved bits
—
—
5
1
Abbreviation
DIVCR
—
—
4
1
—
—
3
1
—
—
2
1
Divide bits 1 and 0
These bits select the
frequency division ratio
R/W
R/W
DIV1
R/W
1
0
Initial Value
H'FC
DIV0
R/W
0
0