DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 540

MCU 5V 128K,PB-FREE 100-TQFP

DF3048X16V

Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048X16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Smart Card Interface
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface.
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detect framing errors.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface. The setting conditions for transmit end (TEND, bit 2), however,
are modified as follows.
Note: An etu (elementary time unit) is the time needed to transmit one bit.
Rev. 7.00 Sep 21, 2005 page 514 of 878
REJ09B0259-0700
Bit 4: ERS
0
1
Bit 2: TEND
0
1
value.
Description
Indicates normal data transmission, with no error signal returned (Initial value)
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads ERS while it is set to 1, then writes 0.
Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Description
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
The DMAC writes data in TDR.
End of transmission
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte
serial character is transmitted (normal transmission)
(Initial value)

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