DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 22

• Manufacturer Part Number: DF3048X16V
• Description: MCU 5V 128K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4 Usage Notes ...................................................................................................................... 531
Section 15 A/D Converter
15.1 Overview........................................................................................................................... 535
15.2 Register Descriptions ........................................................................................................ 539
15.3 CPU Interface.................................................................................................................... 543
15.4 Operation .......................................................................................................................... 544
15.5 Interrupts ........................................................................................................................... 550
15.6 Usage Notes ...................................................................................................................... 550
Section 16 D/A Converter
16.1 Overview........................................................................................................................... 557
16.2 Register Descriptions ........................................................................................................ 560
16.3 Operation .......................................................................................................................... 563
16.4 D/A Output Control .......................................................................................................... 564
16.5 Usage Notes ...................................................................................................................... 564
Section 17 RAM
17.1 Overview........................................................................................................................... 565
Rev. 7.00 Sep 21, 2005 page xx of xxiv
14.3.6 Transmitting and Receiving Data ........................................................................ 524
15.1.1 Features................................................................................................................ 535
15.1.2 Block Diagram..................................................................................................... 536
15.1.3 Input Pins ............................................................................................................. 537
15.1.4 Register Configuration......................................................................................... 538
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 539
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 540
15.2.3 A/D Control Register (ADCR) ............................................................................ 542
15.4.1 Single Mode (SCAN = 0) .................................................................................... 544
15.4.2 Scan Mode (SCAN = 1)....................................................................................... 546
15.4.3 Input Sampling and A/D Conversion Time ......................................................... 548
15.4.4 External Trigger Input Timing............................................................................. 549
16.1.1 Features................................................................................................................ 557
16.1.2 Block Diagram..................................................................................................... 558
16.1.3 Input/Output Pins ................................................................................................. 559
16.1.4 Register Configuration......................................................................................... 559
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 560
16.2.2 D/A Control Register (DACR) ............................................................................ 560
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 562
17.1.1 Block Diagram..................................................................................................... 566
17.1.2 Register Configuration......................................................................................... 566
.................................................................................................................. 565
................................................................................................. 535
................................................................................................. 557