DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 381
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 381 of 907
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Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A
free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When
the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TSR. If the
corresponding OVIE bit is set to 1 in TIER, a CPU interrupt is requested. After the overflow,
the counter continues counting up from H'0000. Figure 10.15 illustrates free-running counting.
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the
corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU interrupt is requested at this
time. After the compare match, TCNT continues counting up from H'0000. Figure 10.16
illustrates periodic counting.
H'FFFF
H'0000
STR0 to
STR4 bit
OVF
TCNT value
Figure 10.15 Free-Running Counter Operation
Section 10 16-Bit Integrated Timer Unit (ITU)
Rev. 7.00 Sep 21, 2005 page 355 of 878
REJ09B0259-0700
Time
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