DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 531
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DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The receive margin in asynchronous mode can therefore be expressed as in equation (1).
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Usage of DMAC: To have the DMAC read RDR, be sure to select the SCI
receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
Restrictions on Usage of the Serial Clock: When transmitting data using an external clock as the
serial clock, an interval of at least 5 states is necessary between clearing the TDRE bit in SSR and
the start (falling edge) of the first transmit clock pulse corresponding to each frame (see figure
13.22). This condition is also needed for continuous transmission. If it is not fulfilled, operational
error will occur.
SCK
TDRE
TXD
Note: *
Ensure that t
M = (0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
D = 0.5, F = 0
M = {0.5 – 1/(2
t*
= 46.875% ............................................................................................. (2)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
X0
5 states.
2N
X1
Figure 13.22 Serial Clock Transmission (Example)
1
) – (L – 0.5) F –
16)}
X2
100%
X3
X4
D – 0.5
N
X5
(1 + F)
Section 13 Serial Communication Interface
X6
Rev. 7.00 Sep 21, 2005 page 505 of 878
X7
100% ................... (1)
t*
Y0
Continuous transmission
Y1
REJ09B0259-0700
Y2
Y3
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