DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 656
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 656 of 907
- Download datasheet (6Mb)
Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
Example of Emulation of Real-Time Flash-Memory Update
Rev. 7.00 Sep 21, 2005 page 630 of 878
REJ09B0259-0700
Small-block
area (SB5)
Notes: 1. When part of RAM (H'FFF000 to H'FFF1FF) is overlapped onto a small-block area in flash
2. When the RAMS bit is set to 1, all flash memory blocks are write-protected and erase-protected,
memory, the overlapped flash memory area cannot be accessed. Access is enabled when the
overlap is cleared.
regardless of the values of bits RAM2 to RAM0. In this state, no transition to program or erase
mode will take place if the P or E bit is set in the flash memory control register (FLMCR). To
actually program or erase a flash memory area, the RAMS bit must be cleared to 0.
H'01F000
H'01F9FF
H'01FA00
H'01FBFF
H'01FDFF
H'01FE00
H'01FFFF
address space
Flash memory
Figure 19.14 Example of RAM Overlap
H'FFEF10
H'FFF000
H'FFF1FF
H'FFF200
H'FFFF0F
Overlapped by RAM
On-chip RAM
area
PP
= 12 V))
Procedure
1. Set the RAME bit to 1 in SYSCR
2. Overlap part of RAM (H'FFF000
3. Perform real-time updates in the
4. After finalization of the update
5. Program the data written in RAM
to enable the on-chip RAM.
to H'FFF1FF) onto the area
requiring real-time update (SB5).
(Set RAMCR bits 3 to 0 to
1101.)
overlapping RAM.
data, clear the RAM overlap (by
clearing the RAMS bit).
addresses H'FFF000 to
H'FFF1FF into the flash memory
area.
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