DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 457
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 457 of 907
- Download datasheet (6Mb)
11.3.4
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample
procedure for setting up non-overlapping TPC output.
ITU setup
Port and
TPC setup
ITU setup
Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)
Non-Overlapping TPC Output
Select non-overlapping groups
Select TPC transfer trigger
Select counting operation
Set next TPC output data
Set next TPC output data
Select interrupt requests
Set initial output data
Enable TPC transfer
Select GR functions
Compare match A?
Set up TPC output
Non-overlapping
Set GR values
Start counter
TPC output
Yes
Section 11 Programmable Timing Pattern Controller
No
1
2
3
4
5
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8
9
10
11
12
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TIER.
The DMAC can also be set up to transfer
data to the next data register.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
In TPMR, select the groups that will operate
in non-overlap mode.
Set the next TPC output values in the NDR
bits.
Set the STR bit to 1 in TSTR to start the timer
counter.
At each IMFA interrupt, write the next output
value in the NDR bits.
Rev. 7.00 Sep 21, 2005 page 431 of 878
REJ09B0259-0700
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