HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 168

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 Memory Management Unit (MMU)
The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data
arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2.
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 4.5.3, OC Address Array.
The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 4.5.4, OC Data Array.
The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address
array. For details, see section 3.7.4, UTLB Address Array.
The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1
and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2.
The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area. For details, see appendix A, Address List.
3.3.2
The SH-4 supports a 29-bit external memory space. The external memory space is divided into
eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous
DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State
Controller (BSC).
Rev.7.00 Oct. 10, 2008 Page 82 of 1074
REJ09B0366-0700
External Memory Space
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Figure 3.5 External Memory Space
Area 7 (reserved area)
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6

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