HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 448

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Name
Data enable 5
Data enable 6
Data enable 7
Ready
Area 0 MPX
interface
specification/
16-bit I/O
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
Endian switchover/
row address strobe
Rev.7.00 Oct. 10, 2008 Page 362 of 1074
REJ09B0366-0700
Signals
WE5/CAS5/
DQM5
WE6/CAS6/
DQM6
WE7/CAS7/
DQM7/REG
RDY
MD6/IOIS16
CKE
BREQ/
BSACK
BACK/
BSREQ
MD3/CE2A *
MD4/CE2B *
MD5/RAS2 *
1
2
3
I/O
O
O
O
I
I
O
I
O
I/O
I/O
When setting synchronous DRAM interface:
When setting synchronous DRAM interface:
When setting synchronous DRAM interface:
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset *
Endian specification in a power-on reset. *
Description
selection signal for D47–D40
When setting DRAM interface: CAS signal for
D47–D40
When setting MPX interface: high-level output
In other cases: write strobe signal for D47–D40
selection signal for D55–D48
When setting DRAM interface: CAS signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
selection signal for D63–D56
When setting DRAM interface: CAS signal for
D63–D56
When setting PCMCIA interface: REG signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
specification signal
When setting PCMCIA interface: CE2A, CE2B
RAS2 when DRAM is connected to area 2
4
: external space area 0 bus width
4