HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 961

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Operand Access Cycle Break Condition Settings
• Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 /
Conditions set: Independent channel A/channel B mode
⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00
⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00
A user break interrupt is not generated on channel A since the instruction access is not a write
cycle.
A user break interrupt is not generated on channel B since instruction access is performed on
an even address.
BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 /
BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080
Conditions set: Independent channel A/channel B mode
⎯ Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00
⎯ Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02
On channel A, a user break interrupt is generated in the event of a longword read at address
H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with
ASID = H'80.
On channel B, a user break interrupt is generated when H'A512 is written by word access to
any address from H'000AB000 to H'000ABFFE with ASID = H'70.
Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
Data: H'00000000 / data mask: H'00000000
Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not
included in conditions)
Bus cycle: operand access, read (operand size not included in conditions)
Data: H'0000A512 / data mask: H'00000000
Bus cycle: operand access, write, word
Data break enabled
Rev.7.00 Oct. 10, 2008 Page 875 of 1074
Section 20 User Break Controller (UBC)
REJ09B0366-0700