HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 236

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Exceptions
5.2
There are three registers related to exception handling. Addresses are allocated to these registers,
and they can be accessed by specifying the P4 address or area 7 address.
1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12-
2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12-
3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit
The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1.
Rev.7.00 Oct. 10, 2008 Page 150 of 1074
REJ09B0366-0700
bit exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
bit exception code. The exception code set in INTEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs. INTEVT can also
be modified by software.
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
EXPEVT and INTEVT
31
TRA
31
Legend:
0: Reserved bits. These bits are always read as 0, and should only be written with 0.
imm: 8-bit immediate data of the TRAPA instruction
0
0
Register Descriptions
Figure 5.1 Register Bit Configurations
12 11
0
10 9
0
Exception code
imm
2
0 0
1 0
0