HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 870

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Smart Card Interface
17.3.3
Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting
side to request retransmission of the data. If an error signal is detected during transmission, the
same data is retransmitted.
The operation sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
2. The transmitting station starts transmission of one frame of data. The data frame starts with a
3. With the smart card interface, the data line then returns to the high-impedance state. The data
Rev.7.00 Oct. 10, 2008 Page 784 of 1074
REJ09B0366-0700
up resistor.
start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
Ds:
D0–D7: Data bits
Dp:
DE:
When there is no parity error
When a parity error occurs
Data Format
Start bit
Parity bit
Error signal
Ds
Ds
D0
D0
Figure 17.3 Smart Card Interface Data Format
D1
D1
Transmitting station output
Transmitting station output
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Dp
Dp
Receiving
station
output
DE