HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 483

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait
states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 5: A0W2
0
1
Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to
be inserted afterwards the second data access in a burst transfer with the burst ROM interface
selected.
Bit 2: A0B2
0
1
Bit 4: A0W1
0
1
0
1
Bit 1: A0B1
0
1
0
1
Bit 3: A0W0
0
1
0
1
0
1
0
1
Bit 0: A0B0
0
1
0
1
0
1
0
1
Inserted Wait States
0
1
2
3
6
9
12
15 (Initial value)
Wait States Inserted from
Second Data Access Onward
0
1
2
3
4
5
6
7 (Initial value)
Rev.7.00 Oct. 10, 2008 Page 397 of 1074
Burst Cycle (Excluding First Cycle)
Section 13 Bus State Controller (BSC)
Description
First Cycle
Description
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
REJ09B0366-0700
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled