HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 385

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.5.3
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2
oscillation stabilization time is required.
1. Make WDT settings as in section 10.5.1.
2. Set the BFC2–BFC0 bits to the desired value.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
4. After the WDT count overflows, clock supply begins within the chip and the processor
10.5.4
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not
performed.
1. Set the BFC2–BFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.5.5
When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is
not performed.
1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.6
The CKIO pin can be switched between clock output and a fixed level setting by means of the
CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is
pulled up.
clock stops and an unstable clock is output to the CKIO pin.
resumes operation. The WDT stops after overflowing.
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
Changing CPU or Peripheral Module Clock Division Ratio
Output Clock Control
Rev.7.00 Oct. 10, 2008 Page 299 of 1074
Section 10 Clock Oscillation Circuits
REJ09B0366-0700