HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 430

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Timer Unit (TMU)
12.2.4
The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each
channel.
When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT,
which continues counting down from the set value.
The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode. The TCOR registers for
channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not
initialized and retain their contents on a manual reset and in standby mode.
12.2.5
The TCNT registers are 32-bit readable/writable registers. There are TCNT registers, one for each
channel.
Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control
register (TCR).
When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the
corresponding timer control register (TCR). At the same time, the timer constant register (TCOR)
value is set in TCNT, and the count-down operation continues from the set value.
Rev.7.00 Oct. 10, 2008 Page 344 of 1074
REJ09B0366-0700
Initial value:
Timer Constant Registers (TCOR)
Timer Counters (TCNT)
R/W:
Bit:
R/W
31
1
R/W
30
1
R/W
29
1
· · · · · · · · · · · · ·
R/W
2
1
R/W
1
1
R/W
0
1