HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 235

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.1
5.1.1
Exception handling is processing handled by a special routine, separate from normal program
processing, that is executed by the CPU in case of abnormal events. For example, if the executing
instruction ends abnormally, appropriate action must be taken in order to return to the original
program sequence, or report the abnormality before terminating the processing. The process of
generating an exception handling request in response to abnormal termination, and passing control
to a user-written exception handling routine, in order to support such functions, is given the
generic name of exception handling.
SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts.
5.1.2
The registers used in exception handling are shown in table 5.1.
Table 5.1
Name
TRAPA exception
register
Exception event
register
Interrupt event
register
Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset.
2. This is the address when using the virtual/physical address space P4 area. The area 7
Overview
Features
Register Configuration
address is the address used when making an access from physical address space area
7 using the TLB.
Exception-Related Registers
Abbrevia-
tion
TRA
EXPEVT
INTEVT
Section 5 Exceptions
R/W
R/W
R/W
R/W
Initial Value *
Undefined
H'0000 0000/
H'0000 0020 *
Undefined
1
1
Rev.7.00 Oct. 10, 2008 Page 149 of 1074
P4
Address *
H'FF00 0020 H'1F00 0020 32
H'FF00 0024 H'1F00 0024 32
H'FF00 0028 H'1F00 0028 32
2
Area 7
Address *
Section 5 Exceptions
REJ09B0366-0700
2
Access
Size