HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 750

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Serial Communication Interface (SCI)
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.9, Bit Rate Register (SCBRR1).
Bit 1: CKS1
0
1
Note: Pck: Peripheral clock
15.2.6
The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCSCR1 can be read or written to by the CPU at all times.
SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and
the TDRE flag in SCSSR1 is set to 1.
Bit 7: TIE
0
1
Note:
Rev.7.00 Oct. 10, 2008 Page 664 of 1074
REJ09B0366-0700
Initial value:
*
Serial Control Register (SCSCR1)
TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it
to 0, or by clearing the TIE bit to 0.
R/W:
Bit:
Bit 0: CKS0
0
1
0
1
Description
Transmit-data-empty interrupt (TXI) request disabled*
Transmit-data-empty interrupt (TXI) request enabled
R/W
TIE
7
0
R/W
RIE
6
0
Description
Pck clock
Pck/4 clock
Pck/16 clock
Pck/64 clock
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0

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