HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 481

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• When DRAM or Synchronous DRAM Interface is Set*
Bit 15: A3W2
0
1
Notes: 1. External wait input is always ignored.
Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states
to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX
interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX
interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).
• When SRAM Interface is Set
Bit 11: A2W2
0
1
2. Inhibited in RAS down mode.
Bit 14: A3W1
0
1
0
1
Bit 10: A2W1
0
1
0
1
Bit 13: A3W0
0
1
0
1
0
1
0
1
Bit 9: A2W0
0
1
0
1
0
1
0
1
DRAM CAS
Assertion Width
1
2
3
4
7
10
13
16
Inserted Wait States
0
1
2
3
6
9
12
15 (Initial value)
Rev.7.00 Oct. 10, 2008 Page 395 of 1074
1
Section 13 Bus State Controller (BSC)
Description
Description
Synchronous DRAM
CAS Latency Cycles
Inhibited
1 *
2
3
4 *
5 *
Inhibited
Inhibited
2
2
2
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
REJ09B0366-0700