LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 105

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

February 2009
Introduction
The LatticeXP2™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced
system I/O standards. This technical note describes the sysIO standards available and how they can be imple-
mented using Lattice’s ispLEVER
sysIO Buffer Overview
The LatticeXP2 sysIO interface contains multiple Programmable I/O Cells (PIC) blocks. Each PIC contains two Pro-
grammable I/Os (PIO), PIOA and PIOB, connected to their respective sysIO Buffers. Two adjacent PIOs can be
joined to provide a differential I/O pair (labeled as “T” and “C”).
Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeXP2 sysIO buffers
supports a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS
strobe signal that is required for interfacing with the DDR memory. One of every 16/18 PIOs in the LatticeXP2 con-
tains a delay element to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe the
DDR data from the memory into input register blocks. For more information on the architecture of the sysIO buffer
please refer to the
The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more detail in TN1138,
Supported sysIO Standards
The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally referenced
standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V stan-
dards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus
maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported
include SSTL and HSTL. Differential standards supported include MLVDS, LVDS, RSDS, BLVDS, LVPECL, differ-
ential SSTL and differential HSTL. Tables 1 and 2 list the sysIO standards supported in LatticeXP2 devices.
Table 8-1. Supported Input Standards
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI 33
HSTL18 Class I, II
HSTL15 Class I
SSTL3 Class I, II
Input Standard
LatticeXP2 Family Data
®
design software.
Sheet.
V
REF
LatticeXP2 sysIO Usage Guide
0.75
8-1
0.9
1.5
—
—
—
—
—
—
—
(Nom.)
LatticeXP2 High Speed I/O
V
CCIO
Technical Note TN1136
1.8
1.5
3.3
1
—
—
—
—
—
—
—
Interface.
(Nom.)
tn1136_01.2