LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 189
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 10-44. PFU Based Distributed Dual Port RAM Timing Waveform - with Output Registers
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger Distributed Memory sizes.
Figure 10-45 shows the Distributed ROM module as generated by IPexpress.
Figure 10-45. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Reset
Data
WE
Q
t
t
t
t
SUWREN_PFU
SUWREN_PFU
SUADDR_PFU
SUDATA_PFU
Data_0
Add_0
OutClockEn
OutClock
t
t
t
Address
HWREN_PFU
HADDR_PFU
HDATA_PFU
Reset
Invalid Data
Data_1
Add_1
10-39
Distributed ROM
PFU-based
t
SUCE_PFU
Add_0
t
HWREN_PFU
LatticeXP2 Memory Usage Guide
t
CORAM_PFU
Q
Data_0
Add_1
Data_1
t
HCE_PFU
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