LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 142
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LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Table 9-11. DCS Modes of Operation
DCS MODE
DCS Timing Diagrams
Each mode performs a unique operation. The clock output timing is determined by input clocks and the edge of the
SEL signal. Figure 9-19 describes the timing of each mode.
Figure 9-19. Timing Diagrams by DCS MODE
Attribute Name
Rising edge triggered, latched state is high
Falling edge triggered, latched state is low
Sel is active high, Disabled output is low
Sel is active high, Disabled output is high
Sel is active low, Disabled output is low
Sel is active low, Disabled output is high
Buffer for CLK0
Buffer for CLK1
CLK0
CLK1
SEL
DCSOUT
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
- Wait for CLK1 rising edge,
- Switch output at CLK0 rising edge
SEL Falling edge:
- Wait for CLK1 falling edge,
- Switch output at CLK0 falling edge
latch output & remain high
latch output & remain low
Description
DCS MODE = POS
DCS MODE = NEG
9-20
SEL Rising edge:
- Wait for CLK0 rising edge,
- Switch output at CLK1 rising edge
SEL Rising edge:
- Wait for CLK0 falling edge,
- Switch output at CLK1 falling edge
latch output & remain high
latch output & remain low
SEL=0
CLK0
CLK0
CLK0
CLK0
CLK0
CLK1
0
1
Output
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
SEL=1
CLK1
CLK1
CLK1
CLK1
CLK0
CLK1
0
1
HIGH_HIGH
HIGH_LOW
LOW_HIGH
LOW_LOW
Value
CLK0
CLK1
POS
NEG
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