LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 187

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create a larger Distributed Memory sizes.
Figure 10-42. Distributed Dual Port RAM Module Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU.
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware prim-
itive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for memory are as per Table 10-15. The table lists the corresponding ports
for the module generated by IPexpress and for the primitive.
Table 10-15. PFU-based Distributed Dual-Port RAM Port Definitions
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-
uration.
Generated Module
Port Name in
RdAddress
RdClockEn
WrClockEn
WrAddress
RdClock
WrClock
Data
WE
Q
RdClockEn
WrClockEn
WrAddress
RdAddress
Port Name in the EBR
RdClock
WrClock
Block Primitive
Reset
Data
WE
WAD[3:0]
RDO[1:0]
RAD[3:0]
DI[1:0]
WCK
WRE
—
—
—
Distributed Dual Port
10-37
PFU based
Memory
Read Clock Enable
Write Clock Enable
Read Address
Write Address
Write Enable
Description
Read Clock
Write Clock
Data Input
Data Out
LatticeXP2 Memory Usage Guide
Q
Rising Clock Edge
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—
—