LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 333
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
ispVM System and ispVME takes care of the detail to program the SPI Flash devices via the JTAG port. The detail
task is shown in the waveform diagram on on
Table 17-7. Description of the Hare-wired JTAG SPI Flash Programming IP
Figure 17-4. Waveform Diagram of the Hare-wired JTAG SPI Flash Programming IP
References
• Lattice Technical Note TN1087,
• Lattice Technical Note TN1141,
• Lattice Technical Note TN1142,
Block #
1
2
3
4
5
6
CCSPIN
SPISO
SCLK
TMS
TDO
TCK
SIPI
TDI
Reset JTAG Port
Send Instruction
Connect
Repeat
Shift Data
Burn Time Delay
???
???
5
1
TLR
Title
TLR
RTI DRS IRS CTR
The standard method to set the JTAG state machine to a known state.
Shift in the PROGRAM_SPI instruction (OPCODE = 0x0X). Indicate bit 0 first shifting direction.
The 4-pin JTAG port is connected to the 4-pin SPI interface. SLCK following TCK indicate
connection is made.
Send in the command to erase a sector or shift in one page of programming data. The FPGA
respond by driving the CSSPIN pin to low to gate on SCLK, SPID0, and SISPI.
Drive the CSSPIN to high to command the SPI Flash device to start the erase or program-
ming action. Wait for the required erase or programming delay time then poll the complete
status. Consult the SPI Flash datasheet for the polling method required.
Loop around to erase by sectors and programming by pages.
RTI DRS IRS CIR
Minimizing System Interruption During Configuration Using TransFR Technology
LatticeXP2 sysCONFIG Usage Guide
LatticeXP2 Configuration Encryption and Security Usage Guide
7
STR
2
E1IR
E1IR
UIR RTI DRS CDR
3
17-15
SIR
UIR RTI DRS CDR
Description
N-1
N-1
SDR
5
LatticeXP2 Dual Boot Feature
4
E1DR
E1DR
6
PDR
SDR
PDR
E2DR UDR DRS
E2DR
IRS TLR
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