LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 163
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL or WRITE THROUGH modes. Each of
these modes affects what data comes out of the port Q of the memory during the write operation followed by the
read operation at the same memory location. The detailed discussions of the WRITE modes and the constraints of
the True Dual Port can be found in Appendix A.
Additionally, users can select to enable the output registers for RAM_DP_TRUE. Figures 10-11 through 10-14
show the internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options.
Figure 10-11. True Dual Port RAM Timing Waveform - NORMAL Mode, without Output Registers
ClockEnA
ClockEnB
AddressA
AddressB
ClockA
WrEnA
ClockB
WrEnB
DataA
DataB
QA
QB
t
t
t
SUADDR_EBR
SUDATA_EBR
SUADDR_EBR
t
SUDATA_EBR
t
t
SUCE_EBR
SUCE_EBR
Data_B0
Data_A0
Add_B0
Add_A0
t
t
SUWREN_EBR
SUWREN_EBR
t
t
t
t
HDATA_EBR
HADDR_EBR
HADDR_EBR
HDATA_EBR
Invalid Data
Invalid Data
Data_A1
Data_B1
Add_B1
Add_A1
t
t
HWREN_EBR
HWREN_EBR
10-13
Add_A0
Add_B0
t
t
CO_EBR
CO_EBR
LatticeXP2 Memory Usage Guide
Data_A0
Data_B0
Add_A1
Add_B1
Data_A1
Data_B1
Add_A2
Add_B2
t
t
HCE_EBR
HCE_EBR
Data_A2
Data_B2
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