LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 270
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 13-12. MAC18X18MACB Packed into a sysDSP Block
sysDSP Blocks in the Report File
To check the configuration of the sysDSP Blocks in your design you can look at the MAP and Post PAR report files.
The MAP report file shows the mapped sysDSP components/primitives in your design. The Post PAR report file
shows the number of components in each sysDSP Block. The report files that follow show how the inferred MAC
was used.
MAP Report File
. MULT18X18MACB
Multiplier
Operation
Operation Registers
--------------------------------------------
Operation Registers
--------------------------------------------
SLOAD DATA1[15:0]*
SLOAD DATA3[15:0]*
MUI18A0[17:0]
MUI18B0[17:0]
MUI18A1[17:0]
MUI18B1[17:0]
MUI18A2[17:0]
MUI18B2[17:0]
MUI18A3[8:0]
MUI18B3[8:0]
Input
Pipeline
Input
Pipeline
addout_17_0:
SRIA[17:0]*
SRIB[17:0]*
SROA[17:0]*
SROB[17:0]*
Notes:
*These signals are optional.
**At least one clock is required.
Unsigned
CLK
CLK
18x18 - 0
18x18 - 1
18x18 - 2
18x18 - 3
CE
CE
CLK[3:0]**
RST[3:0]*
CE[3:0]*
13-11
RST
RST
unused
+/-
+/-
Lattice XP2 sysDSP Usage Guide
SOURCEA[3,1]*
SOURCEB[3,1]*
ADDNSUB[3,1]*
ACCUMSLOAD[3,1]*
SIGNEDA[3,1]*
SIGNEDB[3,1]*
Reg
Reg
Reg
Reg
Out
Out
Out
Out
0
1
2
3
OVERFLOW1
ACCUM1[51:0]
OVERFLOW3
ACCUM3[51:0]
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