LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 264
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LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
Figure 13-5. MAC Mode Advanced Set-up
MULTADDSUB Module
The MULTADDSUB GUI configures multiplier addition/subtraction elements to be packed into the primitives
MULT18X18ADDSUBB or MULT9X9ADDSUBB. The Basic mode, shown in Figure 13-6, consists of an optional
one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accom-
modate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be required. Select
Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or
Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sam-
ple/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in Figure 13-7,
provides finer control over the registers. In the advanced mode, users can control each register with independent
clocks, clock enables and resets. MULTADDSUB inputs can be from 2 to 72 bits.
13-5
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