LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 214

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-12. IDDRMX1A Waveform
IDDRMFX1A
With the IDDRMX1A, the data can enter the FPGA at either the positive or negative edge of the SCLK depending
on the state of the DDRCLKPOL signal. The IDDRMFX1A module includes an additional clock transfer stage that
ensures that the data is transferred at a known edge of the system clock.
Figure 11-13. IDDRMFX1A Symbol
Table 11-4 provides a description of all I/O ports associated with the IDDRMFX1A primitive.
ECLK( DQS shifted 90 deg)
DDR DATA at IDDRMX1A
Case 1: DDRCLKPOL = 0
Case 2: DDRCLKPOL = 1
DDR DATA at I/O
DQS at I/O
SCLK
SCLK
QA
QB
QA
QB
B
C
A
P0
P0
XX
XX
XX
XX
XX
XX
P0
N0
N0
ECLK
RST
CLK1
CLK2
CE
DDRCLKPOL
D
P0
N0
P1
P1
IDDRMFX1A
11-10
P0
N0
P0
N0
P1
N1
N1
N1
P1
P2
P2
QA
QB
LatticeXP2 High-Speed I/O Interface
P1
N1
P1
N1
P2
N2
N2
N2
P2
P3
P3
P2
N2
P2
N2
P3
N3
N3
P3
N3
P4
P4
P3
N3
P3
N3
P4
N4
N4
P4