LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 224

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
All DDR output signals (“ADDR, CMD”, DQS, DQ, DM) are initially aligned to the rising edge of the FPGA clock
inside the FPGA core. The relative phase of the signals may be adjusted in the IOL logic before departing the
FPGA. These adjustments are shown in Figure 11-24.
LatticeXP2 devices contain DDR output and tri-state registers along with the DQSXFER signal generated by the
DQSBUFC that allows easy implementation of the write portion of the DDR memory interfaces. The DDR output
registers can be accessed in the design tools via the ODDRMXA and the ODDRXC primitives.
The DQS signal and the DDR clock outputs are generated using the ODDRXC primitive. As shown in the figure, the
CLKP and DQS signals are generated so that they are 180 degrees in phase with the clock. This is done by con-
necting “1” to the DA input and “0” to the DB inputs of the ODDRXC primitive. Refer to the DDR Generic Software
Primitive section of this document to see the ODDRXC timing waveforms.
The DDR clock output is then fed into a SSTL differential output buffer to generate CLKP and CLKN differential
clocks. Generating the CLKN in this manner prevents any skew between the two signals. When interfacing to
DDR1, SDRAM memory CLKP should be connected to the SSTL25D I/O standard. When interfacing to DDR2
memory, it should be connected to the SSTL18D I/O standard.
The DQSXFER output from the DQSBUFC block is the 90-degree phase shifted clock. This 90-degree phase
shifted clock is used as an input to the ODDRMXA block. The ODDRMXA is used to generate the DQ and DM data
outputs going to the memory. In the ODDRMXA module, the data is first registered using the ECLK or FPGA clock
input and then shifted out using the DQSXFER signal. To ensure that the data going to the memory is center-
aligned to the DQS, the DQSXFER is inverted inside the ODDRXMA primitive. This will generate data that is cen-
ter-aligned to the DQS. Refer to the Software Primitives section of this document for the ODDRXMA timing wave-
forms.
The DDR interface specification for t
times must be met. This is accomplished by ensuring that the CLKP and DQS signals are identical in phase.
The tristate control for the DQS and DQ outputs can also be implemented using the ODDRXC primitive.
Figure 11-24 shows the DDR Write implementation using the DDR primitives.
3. The controller must meet the DDR interface specification for t
4. The DDR output data must be muxed from two SDR streams into a single outgoing DDR data stream.
falling to CLKP rising setup and hold times.
DSS
and t
DSH
parameters defined as DQS falling to CLKP rising setup and hold
11-20
LatticeXP2 High-Speed I/O Interface
DSS
and t
DSH
parameters, defined as DQS