LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 339

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LFXP2-17E-5FN484I

Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-17E-5FN484I

Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Checklist
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
March 2011
June 2007
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
Date
1. Only necessary when CFG=0.
2.2.1
2.2.2
2.2.3
2.2.4
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.1
2.2
2.3
3.1
3.2
3.3
3.4
3.5
1
2
3
Power Supply
Configuration
I/O Pin Assignment
Core Supply VCC @1.2V
Auxiliary Supply V
PLL Supply V
JTAG Supply V
I/O Supply V
Supply Sequencing considerations
Supply Ramp considerations
Power Estimation
Consistency of V
Configuration control and status selections
JTAG Supply and default logic levels
I/O pin assignments around V
DDR Memory pin assignment considerations
True-LVDS pin assignment considerations
HSTL and SSTL pin assignment considerations
PCI clamp requirement considerations
Pull-up or Pull-down on CFG0
Pull-up or Pull-down on CFG1
Pull-up on PROGRAMN
Pull-down on TCK
CCIO0-7
LatticeXP2 Hardware Checklist Item
CCPLL
Version
CCJ
01.0
01.1
CCIO7
CCAUX
from 1.2V to 3.3V
@ 3.3V
from 1.2V to 3.3V
Supply if external SPI Flash is used
@ 3.3V
1
, INITN
CCPLL
1
Initial release.
Added note to “I/O Pin Assignments Around V
1
, DONE
18-5
1
, TOE
Change Summary
LatticeXP2 Hardware Checklist
OK
CCPLL
” text section.
N/A

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