LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 133

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeXP2 sysCLOCK PLL
Lattice Semiconductor
Design and Usage Guide
Figure 9-8. IPexpress Main Window
Configuration Tab
The Configuration Tab lists all user accessible attributes with default values set. Upon completion, clicking Gener-
ate will generate source and constraint files. Users may choose to use the .lpc file to load parameters.
Configuration Modes
There are two modes that can be used to configure the PLL in the Configuration Tab, Frequency Mode and Divider
Mode.
Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the
divider settings. If the output frequency entered is not achievable the nearest frequency will be displayed in the
‘Actual’ text box. After input and output frequencies are entered, clicking the Calculate button will display the
divider values.
Divider Mode: In this mode, the user sets the divider settings with input frequency. Users must choose the CLKOP
Divider value to maximize the f
and achieve optimum PLL performance. After input frequency and divider set-
VCO
tings are set, clicking the Calculate button will display the frequencies. Figure 9-9 shows the Configuration Tab.
9-11