LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 273

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 13-13. Simulink Design
Targeting the sysDSP Block by Instantiating Primitives
The sysDSP Block can be targeted by instantiating the sysDSP Block primitives into the design. The advantage of
instantiating primitives is that it provides access to all ports and sets all available parameters. The disadvantage of
this flow is that all this customization requires extra coding by the user. Appendix A details the syntax for the sys-
DSP Block primitives.
sysDSP Block Control Signal and Data Signal Descriptions
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
RST
SIGNEDA
SIGNEDB
ACCUMSLOAD
ADDNSUB
SOURCEA
SOURCEB
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
Asynchronous reset of selected registers
Dynamic signal: 0 = unsigned, 1 = signed
Dynamic signal: 0 = unsigned, 1 = signed
Dynamic signal: 0 = accumulate, 1 = load
Dynamic signal: 0 = subtract, 1 = add
Dynamic signal: 0 = parallel input, 1 = shift input
Dynamic signal: 0 = parallel input, 1 = shift input
13-14
Lattice XP2 sysDSP Usage Guide