LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 202
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LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Users need not specify data at all address locations. If data is not specified at certain address, the data at that loca-
tion is initialized to 0. IPexpress makes memory initialization possible both through the synthesis and simulation
flows.
FlashBak™ Capability
The LatticeXP2 FPGA family offers FlashBak capability, which is a way to store the data in the EBRs to the Flash
memory upon user command. This protects the user’s data from being lost when the system is powered off. The
FlashBak module (STFA primitive) has a single-command-two-operation process (see Figure 10-61). When the
FlashBak operation is initiated, an erase-UFM-Flash signal is enabled to erase the Flash, followed by the transfer-
to-flash operation. Once the transfer is done, the Flash controller sends a transfer-done signal back to the user
logic. During the FlashBak operation, the EBRs are not accessible. There is no difference between the regular EBR
RAM configuration and the shadow Flash (UFM) EBR RAM configuration in the ispLEVER GUI. The presence of
the STFA (FlashBak) primitive in a design determines the EBR RAM configuration. FlashBak cannot be used if the
soft-error detect (SED) is operating in an Always mode. Since there is no addressing but just a ‘dump’ of all EBR to
Flash, only one STFA module is necessary. Multiple modules are not necessary or allowed.
Figure 10-61. FlashBak Primitive
Figure 10-62. FlashBak Waveform
Table 10-22. STFA Port Descriptions
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
STOREN
UFMFAIL
UFMBUSYN
Port Name
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
Hardware Port Name
Corresponding
storecmdn
fl_busyn
ufm_fail
UFM BUSYN
STOREN
STOREN
Minimum pulse width = 780ns
whether STOREN is released
I/O
1.85µs delay regardless of
O
O
I
Initiates to store the EBR content to Flash
Store to Flash operation failed
Tells the user whether the Flash is in the busy state or not
10-52
UFMBUSYN
UFMFAIL
STFA
LatticeXP2 Memory Usage Guide
Description
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