LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 261

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The sysDSP Block can be configured as:
• One 36x36 Multiplier
• Four 18x18 Multipliers
• Eight 9x9 Multipliers
Note that a sysDSP block can only be configured in one mode at a time.
sysDSP Block Software
Overview
The sysDSP Block of the LatticeXP2 device can be targeted in a number of ways.
• The IPexpress™ tool in the ispLEVER software allows the rapid creation of modules implementing sysDSP ele-
• The coding of certain functions into a design’s HDL and allowing the synthesis tools to Inference the use of a
• The implementation of designs in The MathWorks
• Instantiation of sysDSP primitives directly in the source code
Targeting sysDSP Block Using IPexpress
IPexpress allows you to graphically specify sysDSP elements. Once the element is specified, a HDL file is gener-
ated, which can be instantiated in a design. IPexpress allows users to configure all ports and set all available
parameters. The following modules target the sysDSP Block. For design examples using IPexpress, refer to EXAM-
PLES in the ispLEVER Software (from the Project Navigator pull down-menu, go to File and open Example). The
following four types of elements can be specified via IPexpress:
• MULT (Multiplier)
• MAC (Multiplier Accumulate)
• MULTADDSUB (Multiplier Add/Subtract)
• MULTADDSUBSUM (Multiply Add/Subtract and SUM)
MULT Module
The MULT Module configures elements to be packed into the sysDSP primitives. The Basic mode screen illustrated
in Figure 13-2 consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sys-
DSP Blocks can be spanned to accommodate large multiplications. Additional LUTs may be required if multiple
sysDSP blocks are needed. Select Area/Speed to determine the LUT implementation. The input data format can
be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The
Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced
mode screen, illustrated in Figure 13-3, allows finer control over the register. In the Advanced mode, users can
control each register with independent clocks, clock enables and resets. MULT inputs can be from 2 to 72 bits.
ments. These modules can then be used in HDL designs as appropriate.
sysDSP block.
DSP portion of the ispLEVER design tools will then convert these blocks into HDL as appropriate.
– Basic multiplier, no add/sub/accum/sum blocks
– Two add/sub/accum blocks
– One summation block for adding four multipliers
– Four add/sub blocks
– Two summation blocks
®
Simulink
13-2
®
tool using a Lattice block set. The ispLEVER sys-
Lattice XP2 sysDSP Usage Guide