LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 51

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-13. Supported Output Standards
Hot Socketing
LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os
remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system.
These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access
Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II
HSTL15 Class I
SSTL33 Class I, II
SSTL25 Class I, II
SSTL18 Class I, II
Differential Interfaces
Differential SSTL33, Class I, II
Differential SSTL25, Class I, II
Differential SSTL18, Class I, II
Differential HSTL18, Class I, II
Differential HSTL15, Class I
LVDS
MLVDS
BLVDS
LVPECL
RSDS
LVCMOS33D
1. Emulated with external resistors.
2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This
solution does not require external resistors at the driver.
1, 2
1
1
1
1
Output Standard
1
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA, 16mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA
2mA, 6mA
2-37
Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LatticeXP2 Family Data Sheet
V
CCIO
3.3
3.3
2.5
1.5
1.2
3.3
1.8
1.5
3.3
2.5
3.3
2.5
1.8
1.8
1.5
2.5
2.5
2.5
3.3
2.5
3.3
1.8
—
—
—
—
—
1.8
(Nom.)
Architecture