EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 136
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7–12
Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Note to
(1)
LVPECL I/O Support in the Cyclone III Device Family
Figure 7–8. LVPECL AC-Coupled Termination
Cyclone III Device Handbook, Volume 1
R
P
Figure
= 100
Ω
7–7:
f
Cyclone III Device Family
RSDS Transmitter
Figure 7–7
bottom I/O banks.
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
telecommunications, data communications, and clock distribution. The Cyclone III
device family supports the LVPECL input standard at the dedicated clock input pins
only. The LVPECL receiver requires an external 100-Ω termination resistor between
the two signals at the input buffer.
For more information about the LVPECL I/O standard electrical specification, refer to
the
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone III device family LVPECL input common mode
voltage.
Figure 7–8
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone III device family LVPECL input buffer
specification
CCIO.
Emulated
Cyclone III Device Data Sheet
Transmitter
LVPECL
This standard is used in applications involving video graphics,
shows the RSDS interface with a single resistor network on the top and
shows the AC-coupled termination scheme. The 50-Ω resistors used at the
(Figure
Single Resistor Network
0.1 µF
0.1 µF
7–9).
R
P
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Z 0 = 50
Z 0 = 50
and
Cyclone III LS Device Data Sheet
V ICM
50 Ω
50 Ω
50
50
100 Ω
Cyclone III Device Family
LVPECL Receiver
RSDS Receiver
© December 2009 Altera Corporation
High-Speed I/O Standards Support
chapters.
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