EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 61

• Manufacturer Part Number: EP3C10M164C8N
• Description: IC CYCLONE III FPGA 402MHZ BGA-164
• Manufacturer: Altera
• Series: Cyclone IIIr

Specifications of EP3C10M164C8N

• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 106
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 106
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 164
• Package Type: MBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Operational Modes
Output Registers
Operational Modes
© December 2009
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Altera Corporation
When the signa and signb signals are unused, the Quartus II software sets the
multiplier to perform unsigned multiplication by default.
You can register the embedded multiplier output using output registers in either
18- or 36-bit sections, depending on the operational mode of the multiplier. The
following control signals are available for each output register in the embedded
multiplier:
■
■
■
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
You can use an embedded multiplier block in one of two operational modes,
depending on the application needs:
■
■
You can also use embedded multipliers of the Cyclone III device family to implement
multiplier adder and multiplier accumulator functions, in which the multiplier
portion of the function is implemented using embedded multipliers, and the adder or
accumulator function is implemented in logic elements (LEs).
clock
clock enable
asynchronous clear
One 18-bit × 18-bit multiplier
Up to two 9-bit × 9-bit independent multipliers
Cyclone III Device Handbook, Volume 1
4–5