EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 262
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11–8
Cyclone III Device Handbook, Volume 1
1
Figure 11–3
interface that the WYSIWYG atom enables in your design.
Figure 11–3. Error Detection Block Diagram
The user logic is affected by the soft error failure, thus reading out the 32-bit CRC
signature through the regout should not be relied upon to detect a soft error. You
should rely on the CRC_ERROR output signal itself, because this CRC_ERROR output
signal cannot be affected by a soft error.
To enable the <device>_crcblock WYSIWYG atom, you must name the atom for
each Cyclone III device family accordingly.
80MHz Internal Chip Oscillator
(Saved in the Option Register)
SRAM
shows the error detection block diagram in FPGA devices and shows the
Bits
Pre-Computed CRC
Computation
(1 to 256 Factor)
CRC
Clock Divider
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection
Logic
Logic Array
© December 2009 Altera Corporation
VCC
cyclecomplete
(Shown in BIDIR Mode)
CRC_ERROR
Software Support
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