EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 42
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3–6
Cyclone III Device Handbook, Volume 1
Figure 3–3
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–4
write cycles, respectively.
Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
inclock
shows an address clock enable block diagram. The address register output
and
rden
Figure 3–5
doutn-1
doutn
addressstall
an
address[N]
address[0]
a0
clock
doutn
show the address clock enable waveform during read and
a0
dout0
a1
dout0
dout1
a2
Chapter 3: Memory Blocks in the Cyclone III Device Family
address[N]
address[0]
register
register
dout1
a1
dout1
a3
dout1
dout1
© December 2009 Altera Corporation
address[0]
address[N]
a4
dout1
a4
dout4
a5
dout4
a5
dout5
Overview
a6
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