EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 154
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8–10
Address and Control/Command Pins
Memory Clock Pins
Cyclone III Device Family Memory Interfaces Features
DDR Input Registers
Cyclone III Device Handbook, Volume 1
1
1
Some DDR2 SDRAM and DDR SDRAM devices support error correction coding
(ECC), a method of detecting and automatically correcting errors in data
transmission. In 72-bit DDR2 or DDR SDRAM, there are eight ECC pins and 64 data
pins. Connect the DDR2 and DDR SDRAM ECC pins to a separate DQS or DQ group
in Cyclone III device family. The memory controller needs additional logic to encode
and decode the ECC data.
The address signals and the control or command signals are typically sent at a single
data rate. You can use any of the user I/O pins on all I/O banks of Cyclone III device
family to generate the address and control or command signals to the memory device.
Cyclone III device family does not support QDR II SRAM in the burst length of two.
In DDR2 and DDR SDRAM memory interfaces, the memory clock signals (CK and
CK#) are used to capture the address signals and the control or command signals.
Similarly, QDR II SRAM devices use the write clocks (K and K#) to capture the
address and command signals. The CK/CK# and K/K# signals are generated to
resemble the write-data strobe using the DDIO registers in Cyclone III device family.
CK/CK# pins must be placed on differential I/O pins and cannot be placed on the
same row or column as the DQ pins.
This section describes Cyclone III device family memory interfaces, including DDR
input registers, DDR output registers, OCT, and phase-lock loops (PLLs).
The DDR input registers are implemented with three internal logic element (LE)
registers for every DQ pin. These LE registers are located in the logic array block
(LAB) adjacent to the DDR input pin.
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
© January 2010 Altera Corporation
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