EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 185
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
f
Altera Corporation
The AP configuration scheme in Cyclone III devices supports flash speed grades of
40 MHz and above. However, the AP configuration for all these speed grades must be
capped at 40 MHz. The advantage of faster speed grades is realized when your design
in the Cyclone III device accesses flash memory in user mode.
For more information about the operation of the Numonyx StrataFlash Embedded
Memory P30 and P33 flash memories, search for the keyword “P30” or “P33” on the
Numonyx website (www.numonyx.com) to obtain the P30 or P33 family data sheet.
Single-Device AP Configuration
The following groups of interface pins are supported in Numonyx P30 and P33 flash
memories:
■
■
■
Following are the control signals from the supported parallel flash memories:
■
■
■
■
■
■
The supported parallel flash memories output a control signal (WAIT) to Cyclone III
devices to indicate when synchronous data is ready on the data bus. Cyclone III
devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the
flash memory. A 16-bit bidirectional data bus (DATA[15..0]) provides data transfer
between the Cyclone III device and the flash memory.
The following are the control signals from the Cyclone III device to flash memory:
■
■
■
■
■
■
Control pins
Address pins
Data pins
CLK
active-low reset (RST#)
active-low chip enable (CE#)
active-low output enable (OE#)
active-low address valid (ADV#)
active-low write enable (WE#)
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
Cyclone III Device Handbook, Volume 1
9–25
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