EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 338

• Manufacturer Part Number: EP3C10M164C8N
• Description: IC CYCLONE III FPGA 402MHZ BGA-164
• Manufacturer: Altera
• Series: Cyclone IIIr

Specifications of EP3C10M164C8N

• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 106
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 106
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 164
• Package Type: MBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2–20
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification
Cyclone III Device Handbook, Volume 2
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
(3) t
RISE
FALL
LOCK
(3)
network transmitter is supported at the output pin of all I/O banks.
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
2–28:
20 – 80%,
C
20 – 80%,
C
LOAD
LOAD
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications
(Preliminary)
f
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) t
HSC LK
DUTY
LOCK
= 5 pF
= 5 pF
Modes
(2)
Symbol
LOC K
(input clock
—
—
Table
is the time required for the PLL to lock from the end of device configuration.
2–29:
Min
Modes
—
—
—
—
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
C7 and I7
500
500
Typ
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
Max
500
—
—
C7 and I7
1
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
Min
55
1
—
—
—
—
(Note 1)
Chapter 2: Cyclone III LS Device Data Sheet
,
(2)
C8
Typ
500
500
—
—
© December 2009 Altera Corporation
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
(Part 2 of 2) (Preliminary)
C8
Max
550
—
—
1
Switching Characteristics
402.5
402.5
(Note 1)
Max
320
320
320
320
320
640
640
640
640
640
200
550
55
1
Unit
ms
ps
ps
ps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps
%