EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 309
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications
© January 2010 Altera Corporation
QDRII SRAM
Notes to
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
Standard
Memory
and row I/Os.
clock network.
Table
Table
Parameter
1–33:
1–34:
1.8 V HSTL Class I
1.8 V HSTL Class II
Table 1–34
Duty Cycle Distortion Specifications
Table 1–35
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
OCT Calibration Timing Specification
Table 1–36
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
Power-Up
I/O Standard
Output Duty Cycle
Notes to
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
t
Notes to
(1) OCT calibration takes place after device configuration, before entering user mode.
OCTC AL
and general purpose I/O pins.
I/O standard and current strength.
Table
Table
Symbol
Symbol
(Note 1)
lists the memory output clock jitter specifications for Cyclone III devices.
lists the worst case duty cycle distortion for Cyclone III devices.
lists the duration of calibration for series OCT with calibration at device
1–35:
1–36:
Symbol
t
t
t
JIT(duty)
JIT(per)
JIT(cc)
Lead
1092
1250
Column I/Os (ps)
Duration of series OCT with
calibration at device power-up
Min
45
515
662
Lag
C6
Max
55
Description
-125
-200
-150
Min
Lead
1092
1250
(Note
Min
Row I/Os (ps)
45
C7, I7
1),
(2)
Max
55
Lag
515
662
Max
125
200
150
Cyclone III Device Handbook, Volume 2
(Note 1)
(Note
Min
45
Maximum
Wraparound Mode (ps)
C8, A7
1),
1192
1350
Lead
20
(Part 2 of 2)
(2)
Max
55
Unit
ps
ps
ps
615
762
Lag
Unit
Unit
%
µs
1–25
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