EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 174
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9–14
Cyclone III Device Handbook, Volume 1
In the AS configuration scheme, the serial configuration device latches input and
control signals on the rising edge of DCLK and drives out configuration data on the
falling edge. Cyclone III device family drives out control signals on the falling edge of
DCLK and latch configuration data on the falling edge of DCLK.
In configuration mode, the Cyclone III device family enables the serial configuration
device by driving the nCSO output pin low, which connects to the nCS pin of the
configuration device. The Cyclone III device family uses the DCLK and DATA[1]pins
to send operation commands and read address signals to the serial configuration
device. The configuration device provides data on its DATA pin, which connects to the
DATA[0] input of the Cyclone III device family.
After all the configuration bits are received by the Cyclone III device family, it releases
the open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ resistor.
Initialization begins only after the CONF_DONE signal reaches a logic-high level. All
AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal
pull-up resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by weak internal pull-up resistors. The CONF_DONE pin
must have an external 10-kΩ pull-up resistor for the device to initialize.
The timing parameters for AS mode are not listed here because the t
t
mode listed in
Multi-Device AS Configuration
You can configure multiple Cyclone III device family using a single serial
configuration device. You can cascade multiple Cyclone III device family using the
chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the chain must
have its nCE pin connected to GND. You must connect its nCEO pin to the nCE pin of
the next device in the chain. Use an external 10-kΩ pull-up resistor to pull the nCEO
signal high to its V
device captures all its configuration data from the bitstream, it drives the nCEO pin
low, enabling the next device in the chain. You can leave the nCEO pin of the last
device unconnected or use it as a user I/O pin after configuration if the last device in
the chain is a Cyclone III device family. The nCONFIG, nSTATUS, CONF_DONE, DCLK,
and DATA[0] pins of each device in the chain are connected
STATUS
, t
CF2ST1
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
, and t
Table 9–13 on page
CD2UM
CCIO
level to help the internal weak pull-up resistor. When the first
timing parameters are identical to the timing parameters for PS
9–39.
© December 2009 Altera Corporation
(Figure
CF2CD
9–4).
Configuration Features
, t
CF2ST0
, t
CFG
,
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